Geodesic
Path delay fault test design for circuits obtained by covering ROBDDs with CLBs
Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 69-70.

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Combinational circuits extracted from ROBDDs by covering with CLBs are considered. It has been found that each path delay fault manifests itself as robust one. It means that test for single path delay faults is at the same time test for multiple path delay faults. Deriving test pairs for path delay fault is reduced to finding test pattern for 01(10) fault of arcs radiated from the proper vertex of ROBDDs. 
@article{PDM_2009_10_a35,
     author = {E. A. Nikolaeva and A. Yu. Matrosova},
     title = {Path delay fault test design for circuits obtained by covering {ROBDDs} with {CLBs}},
     journal = {Prikladna\^a diskretna\^a matematika},
     pages = {69--70},
     publisher = {mathdoc},
     number = {10},
     year = {2009},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDM_2009_10_a35/}
}
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E. A. Nikolaeva; A. Yu. Matrosova. Path delay fault test design for circuits obtained by covering ROBDDs with CLBs. Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 69-70. http://geodesic.mathdoc.fr/item/PDM_2009_10_a35/

[1] Drechsler R., Shi J., Fey G., “Synthesis of Fully Testable Circuits from BDDs”, IEEE Trans. On CAD, 23:3 (2001), 440–443

[2] Matrosova A. Yu., Lukovnikova E. S., “Postroenie proveryayuschikh testov dlya odinochnykh i kratnykh neispravnostei na polyusakh elementov skhem, sintezirovannykh na baze PLIS(FPGA)-tekhnologii”, Vestnik Tomskogo gosuniversiteta. Prilozhenie, 2007, no. 23, 229–241