Geodesic
Fault tolerant combinational circuit design
Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 71-72 
S. A. Ostanin. Fault tolerant combinational circuit design. Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 71-72. http://geodesic.mathdoc.fr/item/PDM_2009_10_a36/
@article{PDM_2009_10_a36,
     author = {S. A. Ostanin},
     title = {Fault tolerant combinational circuit design},
     journal = {Prikladna\^a diskretna\^a matematika},
     pages = {71--72},
     year = {2009},
     number = {10},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDM_2009_10_a36/}
}
TY  - JOUR
AU  - S. A. Ostanin
TI  - Fault tolerant combinational circuit design
JO  - Prikladnaâ diskretnaâ matematika
PY  - 2009
SP  - 71
EP  - 72
IS  - 10
UR  - http://geodesic.mathdoc.fr/item/PDM_2009_10_a36/
LA  - ru
ID  - PDM_2009_10_a36
ER  - 
%0 Journal Article
%A S. A. Ostanin
%T Fault tolerant combinational circuit design
%J Prikladnaâ diskretnaâ matematika
%D 2009
%P 71-72
%N 10
%U http://geodesic.mathdoc.fr/item/PDM_2009_10_a36/
%G ru
%F PDM_2009_10_a36

Voir la notice de l'article provenant de la source Math-Net.Ru

Architecture of fault tolerant combinational circuit is suggested. This architecture is based on using a self-checking combinational circuit and a combinational circuit without special properties. The circuit stills properly behavior in the presence of a fault from the fault set defined for it.

[1] Lala Parag K., Digital Circuit Testing and Testability, Academic Press, 1997, 199