Geodesic
Driver output impedance calibration system with comparator unit offset cancellation
Proceedings of the Yerevan State University. Physical and mathematical sciences, Tome 55 (2021) no. 1, pp. 81-89.

Voir la notice de l'article provenant de la source Math-Net.Ru

In modern integrated circuits, the channel length of the transistors is reduced, and the supply voltages are also reduced. But the threshold voltages of the transistors cannot be reduced so quickly due to the physical properties of the materials used, which decreases the operating range of the transistors and makes noises comparable to them. Therefore, it is necessary to eliminate the influence of noise sources in the circuits, in particular, reflections between the transmission line and the output of the transmitter. A system is proposed for calibrating the output impedance of the transmitter based on an accurate external resistor with comparator unit offset voltage compensation. Existing analog and reference frequency based solutions have key disadvantages such as the inability to compensate the offset voltage after the integrated circuit is fabricated, and the distribution of the calibration voltage across the Input/Output device and constant power consumption during the operation. The proposed circuit includes a high-precision digital-to-analog converter to compensate the comparator offset voltage. It generates calibration codes for the pull-up and pull-down parts of the transmitter output buffer, and provides fine tuning of the output impedance. The circuit was modeled using $16~nm$ FinFET process elements and simulated with HSPICE simulator.
Keywords: Input/Output device,transmitter, reflection, offset, output impedance.
Mots-clés : transmission line 
@article{UZERU_2021_55_1_a9,
     author = {V. S. Gevorgyan},
     title = {Driver output impedance calibration system with comparator unit offset cancellation},
     journal = {Proceedings of the Yerevan State University. Physical and mathematical sciences},
     pages = {81--89},
     publisher = {mathdoc},
     volume = {55},
     number = {1},
     year = {2021},
     language = {en},
     url = {http://geodesic.mathdoc.fr/item/UZERU_2021_55_1_a9/}
}
TY  - JOUR
AU  - V. S. Gevorgyan
TI  - Driver output impedance calibration system with comparator unit offset cancellation
JO  - Proceedings of the Yerevan State University. Physical and mathematical sciences
PY  - 2021
SP  - 81
EP  - 89
VL  - 55
IS  - 1
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/UZERU_2021_55_1_a9/
LA  - en
ID  - UZERU_2021_55_1_a9
ER  - 
%0 Journal Article
%A V. S. Gevorgyan
%T Driver output impedance calibration system with comparator unit offset cancellation
%J Proceedings of the Yerevan State University. Physical and mathematical sciences
%D 2021
%P 81-89
%V 55
%N 1
%I mathdoc
%U http://geodesic.mathdoc.fr/item/UZERU_2021_55_1_a9/
%G en
%F UZERU_2021_55_1_a9
V. S. Gevorgyan. Driver output impedance calibration system with comparator unit offset cancellation. Proceedings of the Yerevan State University. Physical and mathematical sciences, Tome 55 (2021) no. 1, pp. 81-89. http://geodesic.mathdoc.fr/item/UZERU_2021_55_1_a9/

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, Second Edition, McGraw-Hill, 2015, 782 pp.

[2] A. S. Sedra, K. C. Smith, Microelectronic Circuits, Oxford University Press, 2014, 1397 pp.

[3] R. J. Baker, CMOS. Circuit Design, Layout, and Simulation, 3rd ed., Wiley. IEEE Press, New York, 2010 | Zbl

[4] Y. Choi, Y. Kim, “A Novel On-chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC”, International Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, USA, 2016, 215–219

[5] H. J. Lee, Y. Kim, “A Process Tolerant Semi-self Impedance Calibration Method for LPDDR4 Memory Controller”, PIEEE. 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, USA, 2015, 1–4 | DOI

[6] M. Bai, X. Wang, J. Jin, T. Mo, “Method Based on Temperature and Process Monitor for LPDDR5 Interface”, 2020 IEEE 15th International Conf. on Solid-State and Integrated Circuit Technology (ICSICT), Kunming, China, 2020, 1–3 | DOI

[7] A. Malkov, D. Vasiounin, O. Semenov, “A Review of PVT Compensation Circuits for Advanced CMOS Technologies”, Circuits System, 2:3 yr 2011, 162–169 | DOI | MR

[8] N. N Buchholz., Hspice Application Manual, Synopsys Inc., 2010, 196 pp.