Geodesic
Graph methods for recognition of CMOS gates in transistor-level circuits
Prikladnaâ diskretnaâ matematika, no. 2 (2024), pp. 43-55

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The paper focuses on the decompilation of a flat transistor circuit in SPICE format into a hierarchical network of logic gates. The problem arises in VLSI layout verification as well as in reverse engineering transistor circuit to redesign integrated circuit and to detect untrusted attachments. The most general case is considered when the extraction of functional level structure from transistor-level circuit is performed without any predetermined cell library. Graph methods for solving some key tasks in this area are proposed. The presented graph methods have been implemented in C++ as a part of a decompilation program, which has been tested using practical transistor-level circuits.
Keywords: CMOS transistor circuit, logic gate recognition, SPICE format.
Mots-clés : subcircuit extraction, graph isomorphism 
@article{PDM_2024_2_a4,
     author = {D. I. Cheremisinov and L. D. Cheremisinova},
     title = {Graph methods for recognition of {CMOS} gates in transistor-level circuits},
     journal = {Prikladna\^a diskretna\^a matematika},
     pages = {43--55},
     publisher = {mathdoc},
     number = {2},
     year = {2024},
     language = {en},
     url = {http://geodesic.mathdoc.fr/item/PDM_2024_2_a4/}
}
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D. I. Cheremisinov; L. D. Cheremisinova. Graph methods for recognition of CMOS gates in transistor-level circuits. Prikladnaâ diskretnaâ matematika, no. 2 (2024), pp. 43-55. http://geodesic.mathdoc.fr/item/PDM_2024_2_a4/