Construction of a~Hamming network based on~a~crossbar with binary memristors
Prikladnaâ diskretnaâ matematika, no. 2 (2018), pp. 105-113.

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The properties of analog and binary memristors (resistors with memory) are described. The memristors can be used for the hardware implementation of neurons synapses. The memristor matrices are called crossbars. The binary memristors, whose resistance takes only two values (maximum and minimum), are based on the switching filament mechanism and are distributed more widely than analog memristors. They are much more stable to statistical fluctuations compared to analog memristors. The Hamming associative memory's hardware realization based on the use of a binary memristors crossbar and CMOS circuitry is proposed. The maximum binary memristor resistance corresponds to the stored reference vector component value $-1$, and the minimum resistance corresponds to the value $+1$. It is shown that the binary memristors crossbar realizes the Hamming network first layer properties according to which the output first layer neuron signal is non-negative. This signal is maximal for a neuron with the reference vector closest to the input vector. For a given reference vector dimension, the relationship between the maximum and minimum binary memristors resistances is obtained. It guarantees the Hamming network first layer correct operation. Simulation in the LTSPICE system of the proposed Hamming memory scheme confirmed its operability.
Keywords: associative Hamming memory, memristor, crossbar, CMOS-technology, LTSPICE.
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     title = {Construction of {a~Hamming} network based on~a~crossbar with binary memristors},
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M. S. Tarkov. Construction of a~Hamming network based on~a~crossbar with binary memristors. Prikladnaâ diskretnaâ matematika, no. 2 (2018), pp. 105-113. http://geodesic.mathdoc.fr/item/PDM_2018_2_a8/

[1] Chua L., “Memristor – the missing circuit element”, IEEE Trans. Circuit Theory, 18 (1971), 507–519 | DOI

[2] Strukov D. B., Snider G. S., Stewart D. R., Williams R. S., “The missing memristor found”, Nature, 453 (2008), 80–83 | DOI

[3] http://www.utmn.ru/presse/teleradiokanal-evrazion/videonovosti-tyumgu/89986/

[4] Pershin Y., Di Ventra M., “Experimental demonstration of associative memory with memristive neural networks”, Neural Networks, 23:7 (2010), 881–886 | DOI

[5] Chua L., “Resistance switching memories are memristors”, Appl. Phys. A: Mater. Sci. Process, 102:4 (2011), 765–783 | DOI

[6] Ho Y., Huang G. M., Li P., “Nonvolatile memristor memory: device characteristics and design applications”, Proc. Int. Conf. ICCAD, 2009, 485–490

[7] Jo S. H., Chang T., Ebong I., et al., “Nanoscale memristor device as synapse in neuromorphic systems”, Nanoletters, 10:4 (2010), 1297–1301 | DOI

[8] Kavehei O., Memristive Devices and Circuits for Computing, Memory, and Neuromorphic Applications, PhD Thesis, The University of Adelaida, Australia, 2011

[9] Lehtonen E., Memristive Computing, Doctoral Thesis, University of Turku, Finland, 2012

[10] Lu W., Kim K.-H., Chang T., Gaba S., “Two-terminal resistive switches (memristors) for memory and logic applications”, Proc. 16th Asia and South Pacific Design Automation Conf., Yokohama, Japan, 2011

[11] Truong S. N., Ham S.-J., Min K.-S., “Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition”, Nanoscale Res. Lett., 9 (2014), 629 http://www.nanoscalereslett.com/content/9/1/629 | DOI

[12] Yakopcic C., Taha T. M., Subramanyam G., Pino R. E., “Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time”, Proc. Int. Joint Conf. Neural Networks (Dallas, Texas, USA, August 4–9, 2013)

[13] Osovskiy S., Neural Networks for Data Processing, Finansy i Statistika, Moscow, 2002, 344 pp. (in Russian)

[14] Zhu X., Yang X., Wu C., et al., “Hamming network circuits based on CMOS/memristor hybrid design”, IEICE Electronics Express, 10:12 (2013), 1–9 | DOI

[15] Lazzaro J., Ryckebusch S., Mahowald M. A., Mead C. A., “Winner-take-all networks of $\mathrm O(n)$ complexity”, Advances in Neural Information Processing Systems, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 1989, 703–711

[16] Volodin V. Ya., Computer Simulation of Electronic Circuitry, BHV-Peterburg Publ., SPb., 2010, 400 pp. (in Russian)