Geodesic
Fault tolerant combinational circuit design
Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 71-72.

Voir la notice de l'article provenant de la source Math-Net.Ru

Architecture of fault tolerant combinational circuit is suggested. This architecture is based on using a self-checking combinational circuit and a combinational circuit without special properties. The circuit stills properly behavior in the presence of a fault from the fault set defined for it. 
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     author = {S. A. Ostanin},
     title = {Fault tolerant combinational circuit design},
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     pages = {71--72},
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     year = {2009},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDM_2009_10_a36/}
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S. A. Ostanin. Fault tolerant combinational circuit design. Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 71-72. http://geodesic.mathdoc.fr/item/PDM_2009_10_a36/

[1] Lala Parag K., Digital Circuit Testing and Testability, Academic Press, 1997, 199