Geodesic
Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 65-66 
V. V. Andreeva; A. Yu. Matrosova; A. V. Mel'nikov; A. V. Morozova. Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method. Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 65-66. http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/
@article{PDM_2009_10_a32,
     author = {V. V. Andreeva and A. Yu. Matrosova and A. V. Mel'nikov and A. V. Morozova},
     title = {Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method},
     journal = {Prikladna\^a diskretna\^a matematika},
     pages = {65--66},
     year = {2009},
     number = {10},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/}
}
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Voir la notice de l'article provenant de la source Math-Net.Ru

Combinational circuit obtained from irredundant system with factorized synthesis method is considered. The conditions of a path delay fault manifestation as robust, non-robust and functional one are detected. Deriving test pairs for path delay fault is reduced to finding test patterns for $a,b$-faults of prime implicants. It allows combining test for single faults of irredundant system (that is test for multiple stuck-at faults at the gate poles of the circuit) with test for path delay faults.

[1] Murgai R., Brayton R., Sangiovani-Vincetelli A., Logic Synthesis for Field Programmable Gate Arrays, Cluver Academic Publisher, 1995, 425

[2] Kohavi I., Kohavi Z., “Detection of multiple faults in combinational logic networks”, IEEE Trans. Comput., 6 (1975), 556–568 | MR