Geodesic
Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 65-66.

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Combinational circuit obtained from irredundant system with factorized synthesis method is considered. The conditions of a path delay fault manifestation as robust, non-robust and functional one are detected. Deriving test pairs for path delay fault is reduced to finding test patterns for $a,b$-faults of prime implicants. It allows combining test for single faults of irredundant system (that is test for multiple stuck-at faults at the gate poles of the circuit) with test for path delay faults. 
@article{PDM_2009_10_a32,
     author = {V. V. Andreeva and A. Yu. Matrosova and A. V. Mel'nikov and A. V. Morozova},
     title = {Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method},
     journal = {Prikladna\^a diskretna\^a matematika},
     pages = {65--66},
     publisher = {mathdoc},
     number = {10},
     year = {2009},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/}
}
TY  - JOUR
AU  - V. V. Andreeva
AU  - A. Yu. Matrosova
AU  - A. V. Mel'nikov
AU  - A. V. Morozova
TI  - Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
JO  - Prikladnaâ diskretnaâ matematika
PY  - 2009
SP  - 65
EP  - 66
IS  - 10
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/
LA  - ru
ID  - PDM_2009_10_a32
ER  - 
%0 Journal Article
%A V. V. Andreeva
%A A. Yu. Matrosova
%A A. V. Mel'nikov
%A A. V. Morozova
%T Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
%J Prikladnaâ diskretnaâ matematika
%D 2009
%P 65-66
%N 10
%I mathdoc
%U http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/
%G ru
%F PDM_2009_10_a32
V. V. Andreeva; A. Yu. Matrosova; A. V. Mel'nikov; A. V. Morozova. Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method. Prikladnaâ diskretnaâ matematika, no. 10 (2009), pp. 65-66. http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/

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