Geodesic
Hardware implementation of one class of 8-bit permutations
Prikladnaya Diskretnaya Matematika. Supplement, no. 12 (2019), pp. 134-137

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The paper studies the issues of implementation of one class of S-Boxes on FPGA and ASIC and compares them with the implementation of arbitrary mappings $V_8 \to V_8$. The way of implementation of arbitrary S-Box is studied. It's shown that any S-Box over $V_8$ can be implemented using 40 LUTs (812 GE). For one class of S-Boxes over $V_8$ with high cryptographic properties, the possibility of their implementation using 19 LUTs (147 GE) is shown.
Keywords: S-Box, FPGA, ASIC.
Mots-clés : permutation 
@article{PDMA_2019_12_a38,
     author = {D. B. Fomin and D. I. Trifonov},
     title = {Hardware implementation of one class of 8-bit permutations},
     journal = {Prikladnaya Diskretnaya Matematika. Supplement},
     pages = {134--137},
     publisher = {mathdoc},
     number = {12},
     year = {2019},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDMA_2019_12_a38/}
}
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D. B. Fomin; D. I. Trifonov. Hardware implementation of one class of 8-bit permutations. Prikladnaya Diskretnaya Matematika. Supplement, no. 12 (2019), pp. 134-137. http://geodesic.mathdoc.fr/item/PDMA_2019_12_a38/