Geodesic
FPGA implementation of FAPKC symmetric equivalent
Prikladnaya Diskretnaya Matematika. Supplement, no. 6 (2013), pp. 36-38

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FPGA implementation of the FAPKC symmetric equivalent (called FASKC) is presented. The throughput/area comparison of the FASKC with the other finite automata cryptosystems is made. The FPGA implementation comparison of the FASKC, AES and other contemporary block ciphers is given.
Keywords: non-linear automaton, invertible with delay automaton, finite automata cryptosystem, FAPKC, PLD, FPGA, VHDL.
Mots-clés : FASKC 
@article{PDMA_2013_6_a18,
     author = {D. S. Kovalev},
     title = {FPGA implementation of {FAPKC} symmetric equivalent},
     journal = {Prikladnaya Diskretnaya Matematika. Supplement},
     pages = {36--38},
     publisher = {mathdoc},
     number = {6},
     year = {2013},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/PDMA_2013_6_a18/}
}
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D. S. Kovalev. FPGA implementation of FAPKC symmetric equivalent. Prikladnaya Diskretnaya Matematika. Supplement, no. 6 (2013), pp. 36-38. http://geodesic.mathdoc.fr/item/PDMA_2013_6_a18/