Geodesic
Data rates assessment on L2–L3 CPU bus and bus between CPU and RAM in modern CPUs
Modelirovanie i analiz informacionnyh sistem, Tome 24 (2017) no. 4, pp. 434-444 Cet article a éte moissonné depuis la source Math-Net.Ru

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In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned. As usual, changes of the currently existing architecture are proposed as a way of increasing CPU performance, data rates on the internal and external CPU interfaces must be known. It would help to assess applicability of proposed solutions and allow to optimize them. This paper is aimed at getting real values of traffic on L2-L3 cache interface inside CPU and CPU-RAM bus load as well as show dependencies of total traffic on the interfaces of interest on the number of active cores, CPU frequency and test type. Measurements methodology using Intel Performance Counter Monitor by Intel is provided and equations that allow to get data rates from internal CPU counters are explained. Both real life and synthetic tests are described. Dependency of total traffic on the number of active cores and dependency of total traffic on CPU frequency are provided as plots. Dependency of total traffic on test type provided as bar plot for multiple CPU frequencies.
Keywords: multicore CPUs, data rates assessment, System-on-Chip, Network-on-Chip, Wireless Network-on-Chip
Mots-clés : NoC, WNoC. 
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     author = {M. S. Komar},
     title = {Data rates assessment on {L2{\textendash}L3} {CPU} bus and bus between {CPU} and {RAM} in modern {CPUs}},
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M. S. Komar. Data rates assessment on L2–L3 CPU bus and bus between CPU and RAM in modern CPUs. Modelirovanie i analiz informacionnyh sistem, Tome 24 (2017) no. 4, pp. 434-444. http://geodesic.mathdoc.fr/item/MAIS_2017_24_4_a3/

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