Geodesic
On verification of PLC-programs written in the LD-language
Modelirovanie i analiz informacionnyh sistem, Tome 19 (2012) no. 2, pp. 138-144

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We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (including timed function blocks) of the IEC 61131-3 standard. We use the Cadence SMV for symbolic model checking. Program properties are written in the linear-time temporal logic LTL.
Keywords: verification, model checking, PLC-programs, Ladder Diagrams. 
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     author = {E. V. Kuz'min and V. A. Sokolov},
     title = {On verification of {PLC-programs} written in the {LD-language}},
     journal = {Modelirovanie i analiz informacionnyh sistem},
     pages = {138--144},
     publisher = {mathdoc},
     volume = {19},
     number = {2},
     year = {2012},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/MAIS_2012_19_2_a9/}
}
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E. V. Kuz'min; V. A. Sokolov. On verification of PLC-programs written in the LD-language. Modelirovanie i analiz informacionnyh sistem, Tome 19 (2012) no. 2, pp. 138-144. http://geodesic.mathdoc.fr/item/MAIS_2012_19_2_a9/