Informacionnye tehnologii i vyčislitelnye sistemy, no. 3 (2007), pp. 79-87
Citer cet article
V. B. Egorov. “Многоэтажная” архитектура процессора. Informacionnye tehnologii i vyčislitelnye sistemy, no. 3 (2007), pp. 79-87. http://geodesic.mathdoc.fr/item/ITVS_2007_3_a7/
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author = {V. B. Egorov},
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journal = {Informacionnye tehnologii i vy\v{c}islitelnye sistemy},
pages = {79--87},
year = {2007},
number = {3},
language = {ru},
url = {http://geodesic.mathdoc.fr/item/ITVS_2007_3_a7/}
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AU - V. B. Egorov
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