Geodesic
Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration
International Journal of Applied Mathematics and Computer Science, Tome 20 (2010) no. 3, pp. 581-589.

Voir la notice de l'article provenant de la source Library of Science

This paper presents research on FPGA based acceleration of HPC applications. The most important goal is to extract a code that can be sped up. A major drawback is the lack of a tool which could do it. HPC applications usually consist of a huge amount of a complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLLs (High Level Languages) such as Mitrion-C (Mohl, 2006). HLLs were invented to make the development of HPRC applications faster. Loop profiling is one of the steps to check if the insertion of an HLL to an existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with minimal initialization of it during the execution of algorithms.
Keywords: HPC, HPRC, loop profiling, Mitrion-C, DFG (data flow graph)
Mots-clés : HPC, HPRC, obliczanie wysokowartościowe, obliczanie rekonfigurowalne, przetwarzanie danych 
@article{IJAMCS_2010_20_3_a12,
     author = {Pietro\'n, M. and Russek, P. and Wiatr, K.},
     title = {Loop profiling tool for {HPC} code inspection as an efficient method of {FPGA} based acceleration},
     journal = {International Journal of Applied Mathematics and Computer Science},
     pages = {581--589},
     publisher = {mathdoc},
     volume = {20},
     number = {3},
     year = {2010},
     language = {en},
     url = {http://geodesic.mathdoc.fr/item/IJAMCS_2010_20_3_a12/}
}
TY  - JOUR
AU  - Pietroń, M.
AU  - Russek, P.
AU  - Wiatr, K.
TI  - Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration
JO  - International Journal of Applied Mathematics and Computer Science
PY  - 2010
SP  - 581
EP  - 589
VL  - 20
IS  - 3
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/IJAMCS_2010_20_3_a12/
LA  - en
ID  - IJAMCS_2010_20_3_a12
ER  - 
%0 Journal Article
%A Pietroń, M.
%A Russek, P.
%A Wiatr, K.
%T Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration
%J International Journal of Applied Mathematics and Computer Science
%D 2010
%P 581-589
%V 20
%N 3
%I mathdoc
%U http://geodesic.mathdoc.fr/item/IJAMCS_2010_20_3_a12/
%G en
%F IJAMCS_2010_20_3_a12
Pietroń, M.; Russek, P.; Wiatr, K. Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration. International Journal of Applied Mathematics and Computer Science, Tome 20 (2010) no. 3, pp. 581-589. http://geodesic.mathdoc.fr/item/IJAMCS_2010_20_3_a12/

[1] Bennett, D., Dellinger, E., Mason, J. and Sundarajan, P. (2006). An FPGA-oriented target language for HLL compilation, Reconfigurable Systems Summer Institute, RSSI 2006, Urbana, IL, USA.

[2] Deng, L., Kim, J.S., Mangalagiri, P., Irick, K., Sobti, K., Kandemir, M., Narayanan, V., Chakrabarti, Ch., Pitsianis, N. and Sun, X. (2009). An automated framework for accelerating numerical algorithms on reconfigurable platform using algorithmic/architectural optimization, IEEE Transactions on Computers 58(12): 1654-1667.

[3] Gasper, P., Herbst, C., McCough, J., Rickett, C. and Stubbendieck, G. (2003). Automatic parallelization of sequential C code, Midwest Instruction and Computing Symposium, Duluth, MN, USA.

[4] Gong, W.,Wang, G. and Kastner, R. (2004). A high performance application representation for reconfigurable systems, Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA, Las Vegas, NV, USA.

[5] Kindratenko, V., Brunner, R. and Myers, A. (2007). Mitrion-C application development on SGI Altix 350/RC100, International Symposium on Field Programmable Custom Computing Machines, FCCM 2007, pp. 239-250.

[6] Kindratenko, V., Myers, A. and Brunner, R. (2006). Exploring coarse- and fine-grain parallelism on a high-performance reconfigurable computer, 2nd Annual Reconfigurable Systems Summer Institute, RSSI 2006, Napa Valley, CA, USA.

[7] Liu, K., Cameron, Ch. and Sarkady, A. (2008). Using Mitrion-C to implement floating-point arithmetic on a Cray XD1 supercomputer, DoD HPCMP Users Group Conference, HPCMP-UGC, Urbana, IL, USA, pp. 391-395.

[8] Memik, S.O., Bozorgzadeh, G., Kastner, R. and Sarrafzadeh, M. (2005). A scheduling algorithm for optimization and planning in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems 10(1).

[9] Messmer, P. and Bodenner R. (2006). Accelerating scentific applications using FPGAs, XCell Journal 10(1): 33-57.

[10] Mohl, S. (2006). The Mitrion-C programming language, Mitrionics Inc., Second Quarter, pp. 70-73, http://www.mitrion.com.

[11] Moseley, T., Grunwald, D., Connors, A., Ramanujam, R., Tovinkere, V. and Peri R. (2006). LoopProf: Dynamic techniques for loop detection and profiling, Proceedings of the 2006 Workshop on Binary Instrumentation and Applications, WBIA, Lund, Sweden.

[12] Pietroń, M.,Wiatr, K. and Russek, P. (2007(a)). Methodology of computing acceleration using reconfigurable logic technology in high performance computing, University of Science and Technology in Cracow Automatica, 2007, pp. 149-156.

[13] Pietroń, M., Russek, P., Wiatr, K., Jamro, E. and Wielgosz, M. (2007(b)). Two electron integrals calculation accelerated with double precision exp() hardware module, Reconfigurable Systems Summer Institute, RSSI, Urbana, IL, USA.

[14] Russek, P. and Wiatr, K. (2006). The prospect of computing acceleration using reconfigurable logic technology in huge computational power systems, Proceedings of the IFAC Workshop on Programable Devices and Embedded Systems, PDeS 2006, Brno, Czech Republic, pp. 44-49.