New inequality relations between depth and delay
Diskretnaya Matematika, Tome 7 (1995) no. 4, pp. 77-85
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We construct a sequence of minimal circuits $S_k$, $k=1,2,\ldots$, such that the delay $T(S_k)$ is considerably less than the depth $D(S_k)$, namely $$ T(S_k)\log_2D(S_k)+6. $$ It is shown that this result cannot be essentially improved.This work is supported by Russian Foundation for Fundamental Investigations, Grant 93–011–1525.