Manatee: A Multicore Interference Analysis Tool for Embedded SoC Evaluation
Computer Science and Information Systems, Tome 22 (2025) no. 2
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Interferences on shared resources are the main factor limiting the employment of multicore architectures in many embedded use cases. Research on these interferences and enhancements, for example in memory hierarchies, could alleviate this restriction. This however requires more awareness of contention for shared resources during the design and development process of System on Chips (SoCs). As an answer we present the concept of a tool which brings this awareness to the RISC-V hardware development framework Chipyard. It extends Chipyard's agile development focus by adding the capabilities for quick feedback on changes regarding shared resource contention. A partial realisation further allows first tests and evaluation on use case basis.
Keywords:
parallel real-time system, memory hierarchy, FPGA prototyping frame-work
Axel Wiedemann; Florian Haas; Sebastian Altmeyer. Manatee: A Multicore Interference Analysis Tool for Embedded SoC Evaluation. Computer Science and Information Systems, Tome 22 (2025) no. 2. http://geodesic.mathdoc.fr/item/CSIS_2025_22_2_a7/
@article{CSIS_2025_22_2_a7,
author = {Axel Wiedemann and Florian Haas and Sebastian Altmeyer},
title = {Manatee: {A} {Multicore} {Interference} {Analysis} {Tool} for {Embedded} {SoC} {Evaluation}},
journal = {Computer Science and Information Systems},
year = {2025},
volume = {22},
number = {2},
url = {http://geodesic.mathdoc.fr/item/CSIS_2025_22_2_a7/}
}
TY - JOUR AU - Axel Wiedemann AU - Florian Haas AU - Sebastian Altmeyer TI - Manatee: A Multicore Interference Analysis Tool for Embedded SoC Evaluation JO - Computer Science and Information Systems PY - 2025 VL - 22 IS - 2 UR - http://geodesic.mathdoc.fr/item/CSIS_2025_22_2_a7/ ID - CSIS_2025_22_2_a7 ER -