Geodesic
Modular-logarithmic coprocessor for massive arithmetic calculations
Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 6 (2017) no. 2, pp. 22-36 Cet article a éte moissonné depuis la source Math-Net.Ru

Voir la notice de l'article

The paper presents a conceptual design of an IP module of mathematical coprocessor. It consists of a set of processing cores of the same kind which perform single-cycle scalar, or vector operations with real numbers. The processed data is represented in the modular logarithmic format that provides two levels of translating the original numbers, namely: the modular level instead of the conventional positional system and the logarithmic level instead of the floating point format. As a result of the research and development, new scientific and technical solutions are proposed that implement the proposed methods of computing and coding data. Owing to this feature a coprocessor has a higher performance, a higher accuracy and a higher level of reliability, as compared to the known analogs. Convert codes in modular-logarithmic number system and vice versa does not introduce significant time delays in a large stream of input data by offering hardware solutions pipelined process of interpolation of the logarithm function and conversion of residual classes system codes. A prototype coprocessor is an FPGA-based IP module. Companies developing general-purpose processors are the target market for this design.
Keywords: residue number system, logarithmic number system, highly reliable computing.
Mots-clés : reconfigurable architecture 
@article{VYURV_2017_6_2_a1,
     author = {I. P. Osinin},
     title = {Modular-logarithmic coprocessor for massive arithmetic calculations},
     journal = {Vestnik \^U\v{z}no-Uralʹskogo gosudarstvennogo universiteta. Seri\^a Vy\v{c}islitelʹna\^a matematika i informatika},
     pages = {22--36},
     year = {2017},
     volume = {6},
     number = {2},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/VYURV_2017_6_2_a1/}
}
TY  - JOUR
AU  - I. P. Osinin
TI  - Modular-logarithmic coprocessor for massive arithmetic calculations
JO  - Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika
PY  - 2017
SP  - 22
EP  - 36
VL  - 6
IS  - 2
UR  - http://geodesic.mathdoc.fr/item/VYURV_2017_6_2_a1/
LA  - ru
ID  - VYURV_2017_6_2_a1
ER  - 
%0 Journal Article
%A I. P. Osinin
%T Modular-logarithmic coprocessor for massive arithmetic calculations
%J Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika
%D 2017
%P 22-36
%V 6
%N 2
%U http://geodesic.mathdoc.fr/item/VYURV_2017_6_2_a1/
%G ru
%F VYURV_2017_6_2_a1
I. P. Osinin. Modular-logarithmic coprocessor for massive arithmetic calculations. Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 6 (2017) no. 2, pp. 22-36. http://geodesic.mathdoc.fr/item/VYURV_2017_6_2_a1/

[1] Top 10 Sites for November 201 } {\tt www.top500.org/lists/2016/11

[2] 754-2008 – IEEE Standard for floating-Point Arithmetic. Revision of ANSI/IEEE Std 754-198 } {\tt ieeexplore.ieee.org/document/4610935

[3] I. P. Osinin, “The Highly-modular Logarithmic Processor with a Reconfigurable Architecture”, Parallel Computational Technologies (PCT'2016): Proceedings of the International Scientific Conference (Arkhangelsk, Russia, March, 28 – April, 1, 2016), Publishing of the South Ural State University, Chelyabinsk, 2016, 642–654

[4] I. P. Osinin, V. S. Knyaz'kov, “Directions of Development of Architecture of Reconfigurable Computing Platforms”, Mathematical modeling of a developing economy, ecology and technology (ECOMOD-2016): Proceedings of the Scientific Conference (Kirov, Russia, July 4–9, 2016), Publishing of the Vyatka State University, Kirov, 2016, 486–495

[5] J. N. Coleman, E. I. Chester, “Arithmetic on the European Logarithmic Microprocessor”, IEEE Transactions on Computers, 49:7 (2000), 702–715 | DOI

[6] R. C. Ismail, R. Hussin, S. A. Muzad, “Interpolator Algorithms for approximating the LNS addition and substraction”, IEEE International Conference on Circuits and Systems (ICCAS) (Kuala Lumpur, 3 – 4 Oct. 2012), 2012, 174–179 | DOI

[7] N. I. Chervyakov, Modular structure of the parallel computing systems neuroprocessor, Publishing Fizmatlit, Moscow, 2003, 288 pp.

[8] A. Omondi, Residue Number System: Theory and Implementation, Imperial College Press, London, 2007, 312 pp.

[9] I. A. Kalmykov, Theoretical bases of calculations in polynomial system of residue classes, focused on building a faulttolerant systems, Publishing North-Caucasian Federal University, Stavropol, 2006, 347 pp.