Geodesic
Estimate of locality of parallel algorithms implemented on GPUs
Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 5 (2016) no. 3, pp. 96-111 Cet article a éte moissonné depuis la source Math-Net.Ru

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The problem of obtaining blocks of operations and threads of parallel algorithm resulting in a smaller number of accesses to global memory and resulting in the efficient use of caches and shared memory graphics processor is investigated. We formulated and proved statements to assess the volume of communication transactions generated by alternative sizing of blocks, as well as to minimize the number of cache misses due to the use of temporal and spatial locality of data. The research is constructive and allows software implementation for practical use.
Keywords: parallel computing, GPU, minimization of communications, temporal locality, spatial locality. 
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     title = {Estimate of locality of parallel algorithms implemented on {GPUs}},
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N. A. Likhoded; M. A. Paliashchuk. Estimate of locality of parallel algorithms implemented on GPUs. Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 5 (2016) no. 3, pp. 96-111. http://geodesic.mathdoc.fr/item/VYURV_2016_5_3_a6/

[1] N.A. Likhoded, M.A. Poleshchuk, “Method of Ranking Tiles Size Parameters of Parallel Algorithm”, Proceedings of the National Academy of Sciences of Belarus, 59:4 (2015), 25–33

[2] M. Kandemir, J. Ramanujam, M. Irwin, V. Narayana, I. Kadayif, A. Parikh, “A Compiler Based Approach for Dynamically Managing Scratch-Pad Memories in Embedded Systems”, IEEE Transactions on Computer-Aided Design, 23:2 (2004), 243–260 | DOI

[3] M. Baskaran, U. Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan, “Automatic Data Movement and Computation Mapping for Multi-Level Parallel Architectures with Explicitly Managed Memories”, Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (Salt Lake City, USA, February 20–23), 2008, 1–10 | DOI

[4] Vl.V. Voevodin, Vad.V. Voevodin, “The Fortunate Locality of Supercomputers”, Open Systems, 2013, no. 9, 12–15

[5] Vl.V. Voevodin, Vad.V. Voevodin, Parallel Computing, BKhV-Peterburg, Sankt-Peterburg, 2002, 608 pp.

[6] J. Xue, W. Cai, “Time-Minimal Tiling when Rise is Larger than Zero”, Parallel Computing, 28:5 (2002), 915–939 | DOI

[7] M. Baskaran, J. Ramanujam, P. Sadayappan, “Automatic C-to-CUDA Code Generation for Affine Programs”, Proceedings of the Compiler Construction, 19th International Conference. Part of the Joint European Conferences on Theory and Practice of Software (Paphos, Cyprus, March 20–28), 2010, 244–263 | DOI

[8] U. Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan, “Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model”, Lecture Notes in Computer Science, 2008, no. 4959, 132–146 | DOI

[9] G. Venkataraman, S. Sahni, S. Mukhopadhyaya, “A Blocked All-Pairs Shortest-Paths Algorithm”, J. Exp. Algorithmics, 2003, no. 8, 2.2 | DOI

[10] G.J. Katz, J. Kider, “All-Pairs Shortest-Paths for Large Graphs on the GPU”, Proceedings of the 23rd ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware (Sarajevo, Bosnia and Herzegovina), Eurographics Association, 2008, 47–55

[11] B.D. Lund, J.W. Smith, “A Multi-Stage CUDA Kernel for Floyd-Warshall”, CoRR abs/1001.4108, 2010