Geodesic
Automatic mapping programs onto a processor with an FPGA accelerator
Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 3 (2014) no. 2, pp. 117-121 Cet article a éte moissonné depuis la source Math-Net.Ru

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A problem of automatic high level program mapping onto a CPU with an FPGA accelerator is considered in this work. For such a mapping an HDL code generator from a parallelizing system's internal representation is being developed and used.
Keywords: social network analysis, information retrieval, data mining, expert finding, popularity analysispeline computing, high-level synthesis, parallelizing compiler, FPGA, VHDL. 
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D. V. Dubrov; A. S. Roshal; B. Ya. Steinberg; R. B. Steinberg. Automatic mapping programs onto a processor with an FPGA accelerator. Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 3 (2014) no. 2, pp. 117-121. http://geodesic.mathdoc.fr/item/VYURV_2014_3_2_a9/

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