Geodesic
Automatic mapping programs onto a processor with an FPGA accelerator
Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 3 (2014) no. 2, pp. 117-121

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A problem of automatic high level program mapping onto a CPU with an FPGA accelerator is considered in this work. For such a mapping an HDL code generator from a parallelizing system's internal representation is being developed and used.
Keywords: social network analysis, information retrieval, data mining, expert finding, popularity analysispeline computing, high-level synthesis, parallelizing compiler, FPGA, VHDL. 
@article{VYURV_2014_3_2_a9,
     author = {D. V. Dubrov and A. S. Roshal and B. Ya. Steinberg and R. B. Steinberg},
     title = {Automatic mapping programs onto a processor with an {FPGA} accelerator},
     journal = {Vestnik \^U\v{z}no-Uralʹskogo gosudarstvennogo universiteta. Seri\^a Vy\v{c}islitelʹna\^a matematika i informatika},
     pages = {117--121},
     publisher = {mathdoc},
     volume = {3},
     number = {2},
     year = {2014},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/VYURV_2014_3_2_a9/}
}
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D. V. Dubrov; A. S. Roshal; B. Ya. Steinberg; R. B. Steinberg. Automatic mapping programs onto a processor with an FPGA accelerator. Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ Vyčislitelʹnaâ matematika i informatika, Tome 3 (2014) no. 2, pp. 117-121. http://geodesic.mathdoc.fr/item/VYURV_2014_3_2_a9/