Geodesic
Russian 3D-torus interconnect with globally addressable memory support
Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ, Matematičeskoe modelirovanie i programmirovanie, no. 6 (2010), pp. 41-53 Cet article a éte moissonné depuis la source Math-Net.Ru

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This paper gives the overview and early results of prototyping of the 3D-torus interconnect developed in NICEVT, Moscow. This interconnect was designed to be equally effective in small-size computing clusters and petascale systems. The key features of the interconnect are high fault-tolerance, high message rate per core supported by host adapter and hardware support for globally addressable memory provided via SHMEM parallel programming library.
Keywords: interconnection network, supercomputer, globally addressable memory.
Mots-clés : 3D-torus 
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     title = {Russian {3D-torus} interconnect with globally addressable memory support},
     journal = {Vestnik \^U\v{z}no-Uralʹskogo gosudarstvennogo universiteta. Seri\^a, Matemati\v{c}eskoe modelirovanie i programmirovanie},
     pages = {41--53},
     year = {2010},
     number = {6},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/VYURU_2010_6_a4/}
}
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A. A. Korzh; D. V. Makagon; A. A. Borodin; I. A. Zhabin; E. R. Kushtanov; E. L. Syromyatnikov; E. V. Cheryomushkina. Russian 3D-torus interconnect with globally addressable memory support. Vestnik Ûžno-Uralʹskogo gosudarstvennogo universiteta. Seriâ, Matematičeskoe modelirovanie i programmirovanie, no. 6 (2010), pp. 41-53. http://geodesic.mathdoc.fr/item/VYURU_2010_6_a4/

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