Geodesic
An approach to the construction of a network processing unit
Modelirovanie i analiz informacionnyh sistem, Tome 26 (2019) no. 1, pp. 39-62.

Voir la notice de l'article provenant de la source Math-Net.Ru

The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented - NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.
Keywords: network processor, network processing unit, switch, computer networks, SDN, computer architecture, simulation modeling, Open Flow protocol. 
@article{MAIS_2019_26_1_a3,
     author = {S. O. Bezzubtsev and V. V. Vasin and D. Yu. Volkanov and Sh. R. Zhailauova and V. A. Miroshnik and Yu. A. Skobtsova and R. L. Smelyansky},
     title = {An approach to the construction of a network processing unit},
     journal = {Modelirovanie i analiz informacionnyh sistem},
     pages = {39--62},
     publisher = {mathdoc},
     volume = {26},
     number = {1},
     year = {2019},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/MAIS_2019_26_1_a3/}
}
TY  - JOUR
AU  - S. O. Bezzubtsev
AU  - V. V. Vasin
AU  - D. Yu. Volkanov
AU  - Sh. R. Zhailauova
AU  - V. A. Miroshnik
AU  - Yu. A. Skobtsova
AU  - R. L. Smelyansky
TI  - An approach to the construction of a network processing unit
JO  - Modelirovanie i analiz informacionnyh sistem
PY  - 2019
SP  - 39
EP  - 62
VL  - 26
IS  - 1
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/MAIS_2019_26_1_a3/
LA  - ru
ID  - MAIS_2019_26_1_a3
ER  - 
%0 Journal Article
%A S. O. Bezzubtsev
%A V. V. Vasin
%A D. Yu. Volkanov
%A Sh. R. Zhailauova
%A V. A. Miroshnik
%A Yu. A. Skobtsova
%A R. L. Smelyansky
%T An approach to the construction of a network processing unit
%J Modelirovanie i analiz informacionnyh sistem
%D 2019
%P 39-62
%V 26
%N 1
%I mathdoc
%U http://geodesic.mathdoc.fr/item/MAIS_2019_26_1_a3/
%G ru
%F MAIS_2019_26_1_a3
S. O. Bezzubtsev; V. V. Vasin; D. Yu. Volkanov; Sh. R. Zhailauova; V. A. Miroshnik; Yu. A. Skobtsova; R. L. Smelyansky. An approach to the construction of a network processing unit. Modelirovanie i analiz informacionnyh sistem, Tome 26 (2019) no. 1, pp. 39-62. http://geodesic.mathdoc.fr/item/MAIS_2019_26_1_a3/

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