Voir la notice de l'article provenant de la source Math-Net.Ru
@article{MAIS_2012_19_6_a3, author = {D. Yu. Volkanov and V. A. Zakharov and D. A. Zorin and I. V. Konnov and V. V. Podymov}, title = {On the {Designing} of {Model} {Checkers} for {Real-Time} {Distributed} {Systems}}, journal = {Modelirovanie i analiz informacionnyh sistem}, pages = {45--56}, publisher = {mathdoc}, volume = {19}, number = {6}, year = {2012}, language = {ru}, url = {http://geodesic.mathdoc.fr/item/MAIS_2012_19_6_a3/} }
TY - JOUR AU - D. Yu. Volkanov AU - V. A. Zakharov AU - D. A. Zorin AU - I. V. Konnov AU - V. V. Podymov TI - On the Designing of Model Checkers for Real-Time Distributed Systems JO - Modelirovanie i analiz informacionnyh sistem PY - 2012 SP - 45 EP - 56 VL - 19 IS - 6 PB - mathdoc UR - http://geodesic.mathdoc.fr/item/MAIS_2012_19_6_a3/ LA - ru ID - MAIS_2012_19_6_a3 ER -
%0 Journal Article %A D. Yu. Volkanov %A V. A. Zakharov %A D. A. Zorin %A I. V. Konnov %A V. V. Podymov %T On the Designing of Model Checkers for Real-Time Distributed Systems %J Modelirovanie i analiz informacionnyh sistem %D 2012 %P 45-56 %V 19 %N 6 %I mathdoc %U http://geodesic.mathdoc.fr/item/MAIS_2012_19_6_a3/ %G ru %F MAIS_2012_19_6_a3
D. Yu. Volkanov; V. A. Zakharov; D. A. Zorin; I. V. Konnov; V. V. Podymov. On the Designing of Model Checkers for Real-Time Distributed Systems. Modelirovanie i analiz informacionnyh sistem, Tome 19 (2012) no. 6, pp. 45-56. http://geodesic.mathdoc.fr/item/MAIS_2012_19_6_a3/
[1] A. David, M. O. Moller, From HUppaal to Uppaal: a translation from hierarchical timed automata to flat timed automata, BRICS Report Series RS-01-11, Department of Computer Science, University of Aarhus, March 2001
[2] M. E. Lakhnech, M. Siegal, “Hierarchical automata as model for statechart”, Lecture Notes in Computer Science, 1345, 1997, 187–196 | MR
[3] Chen Hai-yan, Dong Wei, Wang Huo-wang, “Verify UML statechart with SMV”, Wuhan University Journal of Natural Science, 6:1–2 (2001), 183–190
[4] T. Jussila, J. Dubrovin, T. Junttila, T. Latvala, I. Pores, “Model checking dynamic and hierarchical UML state machines”, Proc. of the 3rd Workshop on Model Design and Validation, 2006
[5] D. Latella, I. Majzik, M. Massink, “Automatic verification of a behavioural subset of UML statechart diagrams using SPIN model-checker”, Formal Aspects of Computations, 11 (1999) | Zbl
[6] J. Lilius, I. Paltor, vUML: a Tool for Verifying UML Models, Technical Report TUCS-272, Turku Centre for Computer Science, 1999
[7] I. Ober, S. Graf, I. Ober, “Validating timed (UML) models by simulation and verification”, SVERTS 2003, Proc. of the Workshop on Specification and Validation of UML models for Real Time and Embedded Systems, 2003
[8] G. Behrmann, A. David, K. G. Larsen, “A Tutorial on Uppaal”, Lecture Notes in Computer Science, 3185, 2004, 200–236 | Zbl
[9] J. Bengtsson, K. G. Larsen, F. Larsson, P. Pettersson, W. Yi, “UPPAAL — a Tool Suite for Automatic Verification of Real-Time Systems”, Lecture Notes in Computer Science, 1066, 1996, 232–243
[10] A. David, M. O. Moller, W. Yi, Verification of UML statechart with real-time extensions, IT Tech. Rep. 2003-009, Dep. of Information Technology, Uppsala University, Uppsala, 2003
[11] A. L. N. Muniz, A. M. S. Andrade, G. Lima, “Integrating UML and UPPAAL for designing, specifying and verifying component-based real-time systems”, Innovation in Software and System Engineering, 2009
[12] R. Alur, D. L. Dill, “Automata for modeling real-time systems”, Lecture Notes in Computer Science, 443, 1990, 322–335 | MR | Zbl
[13] R. Alur, D. L. Dill, “A theory of timed automata”, Theoretical Computer Science, 126 (1994), 183–235 | MR | Zbl
[14] M. C. Browne, M. C. Clarke, O. Grumberg, “Characterizing finite Kripke structures in propo-sitional temporal logics”, Theoretical Computer Science, 59:1–2 (1988), 115–131 | MR | Zbl
[15] M. V. Chistolinov, I. V. Epatko, A. G. Bahmurov, R. L. Smelyansky, V. A. Zakharov, K. Winter, Y. Usenko, “Towards a unified toolset for embedded systems development”, Problems of Programming, Proc. of the conference UKRPROG-2000, v. 1, 2000, 316–322