Geodesic
Embedded test and debug system with JTAG interface for CMOS digital IC
Informacionnye tehnologii i vyčislitelnye sistemy, no. 4 (2015), pp. 22-27.

Voir la notice de l'article provenant de la source Math-Net.Ru

Proposed test and debug system based on scan technology for CMOS digital IC. Designed debug system makes a “snapshot” of logic states of all triggers in VLSI and provides transfer of test data to tester by JTAG. Proposed debug structure is low-area (0.2% overhead) which is 0.1% lower than compared system.
Mots-clés : VLSI debug
Keywords: JTAG, design-for-debug. 
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     author = {M. S. Ladnushkin},
     title = {Embedded test and debug system with {JTAG} interface for {CMOS} digital {IC}},
     journal = {Informacionnye tehnologii i vy\v{c}islitelnye sistemy},
     pages = {22--27},
     publisher = {mathdoc},
     number = {4},
     year = {2015},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/ITVS_2015_4_a2/}
}
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M. S. Ladnushkin. Embedded test and debug system with JTAG interface for CMOS digital IC. Informacionnye tehnologii i vyčislitelnye sistemy, no. 4 (2015), pp. 22-27. http://geodesic.mathdoc.fr/item/ITVS_2015_4_a2/