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Interconnect synthesis in high speed digital VLSI routing.
International journal of open problems in computer science and mathematics, Tome 2 (2009) no. 3, p. 383 Cet article a éte moissonné depuis la source European Digital Mathematics Library

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Classification : 93A30, 93C80, 93B11
Keywords: detailed routing, global routing, high speed digital VLSI design, interconnect synthesis, interval labeling scheme, line search routers, sequential routing 
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     author = {Sayed, Moustafa A. and Maksoud, Ehab Y.Abdel},
     title = {Interconnect synthesis in high speed digital {VLSI} routing.},
     journal = {International journal of open problems in computer science and mathematics},
     pages = {383},
     year = {2009},
     volume = {2},
     number = {3},
     zbl = {1209.93027},
     language = {en},
     url = {http://geodesic.mathdoc.fr/item/IJOPCM_2009__2_3_227238/}
}
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Sayed, Moustafa A.; Maksoud, Ehab Y.Abdel. Interconnect synthesis in high speed digital VLSI routing.. International journal of open problems in computer science and mathematics, Tome 2 (2009) no. 3, p. 383. http://geodesic.mathdoc.fr/item/IJOPCM_2009__2_3_227238/