Geodesic
Remarks on hardware implementation of image processing algorithms
International Journal of Applied Mathematics and Computer Science, Tome 18 (2008) no. 1, pp. 105-110

Voir la notice de l'article provenant de la source Library of Science

Image processing in industrial vision systems requires both real-time speed and robustness. Modern computers, which fulfill the first demand, are sensitive to hard industrial environment conditions and require considerable amounts of energy. Programmable logic chips are available, which can realize many simple, still time-consuming operations in a parallel or a pipelined manner. The paper discusses particular features of the pipelined architecture and presents selected techniques of implementing early image processing procedures in hardware.
Keywords: on-line image processing, real-time, hardware, pipeline, programmable logic
Mots-clés : logika programowalna, przetwarzanie obrazu, czas rzeczywisty, sprzęt komputerowy 
@article{IJAMCS_2008_18_1_a9,
     author = {Wnuk, M.},
     title = {Remarks on hardware implementation of image processing algorithms},
     journal = {International Journal of Applied Mathematics and Computer Science},
     pages = {105--110},
     publisher = {mathdoc},
     volume = {18},
     number = {1},
     year = {2008},
     language = {en},
     url = {http://geodesic.mathdoc.fr/item/IJAMCS_2008_18_1_a9/}
}
TY  - JOUR
AU  - Wnuk, M.
TI  - Remarks on hardware implementation of image processing algorithms
JO  - International Journal of Applied Mathematics and Computer Science
PY  - 2008
SP  - 105
EP  - 110
VL  - 18
IS  - 1
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/IJAMCS_2008_18_1_a9/
LA  - en
ID  - IJAMCS_2008_18_1_a9
ER  - 
%0 Journal Article
%A Wnuk, M.
%T Remarks on hardware implementation of image processing algorithms
%J International Journal of Applied Mathematics and Computer Science
%D 2008
%P 105-110
%V 18
%N 1
%I mathdoc
%U http://geodesic.mathdoc.fr/item/IJAMCS_2008_18_1_a9/
%G en
%F IJAMCS_2008_18_1_a9
Wnuk, M. Remarks on hardware implementation of image processing algorithms. International Journal of Applied Mathematics and Computer Science, Tome 18 (2008) no. 1, pp. 105-110. http://geodesic.mathdoc.fr/item/IJAMCS_2008_18_1_a9/

[1] Drzazga A., Hajdul J., Malec J. and Wnuk M. (1983). Hardware image preprocessor, Technical Report,Wrocław University of Technology (in Polish).

[2] Dudani S., Breeding K. and McGhee R. (1977). Aircraft identification by moment invariants, IEEE Transactions on Computers, 26(1): 39-46.

[3] SGS-THOMSONMicroelectronics (1994). IMSA110 Image and Signal Processing Sub-system, http://www.datasheetcatalog.com.

[4] Texas Instruments Europe (1997). Implementation of an Image Processing Library for the TMS320C8x, BPRA059, http://www.datasheetcatalog.com.

[5] Xilinx, Inc. (2007). Spartan-3A DSP FPGA Family: Complete Data Sheet, DS610, http://www.datasheetcatalog.com.