Geodesic
Designing digital signal processing extension for multipurpose microprocessor
Fundamentalʹnaâ i prikladnaâ matematika, Tome 12 (2006) no. 8, pp. 159-180.

Voir la notice de l'article provenant de la source Math-Net.Ru

The digital signal processing extension for the multipurpose 64 bit processor K 64-SMP designed by the Institute for System Research of the Russian Academy of Science is discussed. The proposed extension increases the processor efficiency for signal processing by a factor of 3. We discuss also the stream programming scheme utilized in the extension programming. 
@article{FPM_2006_12_8_a6,
     author = {A. A. Lesnykh and I. A. Shirokov},
     title = {Designing digital signal processing extension for multipurpose microprocessor},
     journal = {Fundamentalʹna\^a i prikladna\^a matematika},
     pages = {159--180},
     publisher = {mathdoc},
     volume = {12},
     number = {8},
     year = {2006},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/FPM_2006_12_8_a6/}
}
TY  - JOUR
AU  - A. A. Lesnykh
AU  - I. A. Shirokov
TI  - Designing digital signal processing extension for multipurpose microprocessor
JO  - Fundamentalʹnaâ i prikladnaâ matematika
PY  - 2006
SP  - 159
EP  - 180
VL  - 12
IS  - 8
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/FPM_2006_12_8_a6/
LA  - ru
ID  - FPM_2006_12_8_a6
ER  - 
%0 Journal Article
%A A. A. Lesnykh
%A I. A. Shirokov
%T Designing digital signal processing extension for multipurpose microprocessor
%J Fundamentalʹnaâ i prikladnaâ matematika
%D 2006
%P 159-180
%V 12
%N 8
%I mathdoc
%U http://geodesic.mathdoc.fr/item/FPM_2006_12_8_a6/
%G ru
%F FPM_2006_12_8_a6
A. A. Lesnykh; I. A. Shirokov. Designing digital signal processing extension for multipurpose microprocessor. Fundamentalʹnaâ i prikladnaâ matematika, Tome 12 (2006) no. 8, pp. 159-180. http://geodesic.mathdoc.fr/item/FPM_2006_12_8_a6/

[3] Bakhvalov N. S., Chislennye metody, Nauka, M., 1973

[4] Betelin V. B., Bobkov S. G., Zendrikova S. A., Kravchenko A. A., Kushnirenko A. G., Nikolaev V. K., Teoreticheskie otsenki effektivnosti superEVM s raspredelennoi pamyatyu, NIISI RAN 2003, M.

[5] Vyukova V. V., Galatenko V. A., Samborskii S. V., Shumakov S. M., Opisanie VLIW-arkhitektury v optimiziruyuschem postprotsessore Informatsionnaya bezopasnost. Instrumentalnye sredstva programmirovaniya. Bazy dannykh, ed. V. B. Betelin, NIISI RAN, M., 2001

[6] Vyukova V. V., Galatenko V. A., Samborskii S. V., Shumakov S. M., O probleme optimizatsii koda dlya protsessornykh arkhitektur s yavnym parallelizmom, IPU RAN, M., 2001

[7] Korneev V. V., Parallelnye vychislitelnye sistemy, Nolidzh, M., 1999

[8] Kushnirenko A. G., Lebedev G. V., Programmirovanie dlya matematikov, Nauka, M., 1988

[9] Lesnykh A. A., Shirokov I. A., Otsenki proizvoditelnosti superEVM na osnove soprotsessora veschestvennoi arifmetiki na zadachakh obrabotki signalov, NIISI RAN, M., 2005

[10] Dongarra J. J., Performance of various computers using standard linear equations software, Technical report UT-CS-89-85, University of Tennessee, Knoxville, 1989; http://www.netlib.org/benchmark/performance.ps

[11] Dongarra J. J., Duff I. S., Sorensen D. C., Van der Vorst H. A., Numerical Linear Algebra for High-Performance Computers, Software Environments Tools, 7, SIAM, Philadelphia, 1998 | MR | Zbl

[12] Hwang K., Xu Z., Scalable parallel computing, McGraw-Hill, 1998 | Zbl