On the complexity of fanout-bounded parallel prefix circuits
Diskretnyj analiz i issledovanie operacij, Tome 31 (2024) no. 4, pp. 151-167 Cet article a éte moissonné depuis la source Math-Net.Ru

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We prove that the complexity of a universal depth-$n$ parallel prefix circuit on $2^n$ inputs with fanout bounded by $2$ is at least $0.75(n-1)2^{n}.$ We also propose a number of simple constructions and upper complexity bounds on fanout-$2$ prefix circuits of depth $n+k.$ Illustr. 4, bibliogr. 14.
Keywords: parallel prefix circuit, fanout-bounded circuit, circuit complexity, circuit depth.
@article{DA_2024_31_4_a7,
     author = {I. S. Sergeev},
     title = {On the complexity of fanout-bounded parallel~prefix~circuits},
     journal = {Diskretnyj analiz i issledovanie operacij},
     pages = {151--167},
     year = {2024},
     volume = {31},
     number = {4},
     language = {ru},
     url = {http://geodesic.mathdoc.fr/item/DA_2024_31_4_a7/}
}
TY  - JOUR
AU  - I. S. Sergeev
TI  - On the complexity of fanout-bounded parallel prefix circuits
JO  - Diskretnyj analiz i issledovanie operacij
PY  - 2024
SP  - 151
EP  - 167
VL  - 31
IS  - 4
UR  - http://geodesic.mathdoc.fr/item/DA_2024_31_4_a7/
LA  - ru
ID  - DA_2024_31_4_a7
ER  - 
%0 Journal Article
%A I. S. Sergeev
%T On the complexity of fanout-bounded parallel prefix circuits
%J Diskretnyj analiz i issledovanie operacij
%D 2024
%P 151-167
%V 31
%N 4
%U http://geodesic.mathdoc.fr/item/DA_2024_31_4_a7/
%G ru
%F DA_2024_31_4_a7
I. S. Sergeev. On the complexity of fanout-bounded parallel prefix circuits. Diskretnyj analiz i issledovanie operacij, Tome 31 (2024) no. 4, pp. 151-167. http://geodesic.mathdoc.fr/item/DA_2024_31_4_a7/

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