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SPC5: an efficient SpMV framework vectorized using ARM SVE and x86 AVX-512
Computer Science and Information Systems, Tome 21 (2024) no. 1.

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The sparse matrix/vector product (SpMV) is a fundamental operation in scientific computing. Having access to an efficient SpMV implementation is therefore critical, if not mandatory, to solve challenging numerical problems. The ARM-based AFX64 CPU is a modern hardware component that equips one of the fastest supercomputers in the world. This CPU supports the Scalable Vector Extension (SVE) vectorization technology, which has been less investigated than the classic x86 instruction set architectures. In this paper, we describe how we ported the SPC5 SpMV framework on AFX64 by converting AVX512 kernels to SVE. In addition, we present performance results by comparing our kernels against a standard CSR kernel for both Intel-AVX512 and Fujitsu-ARM-SVE architectures.
Keywords: SpMV, vectorization, AVX-512, SVE 
@article{CSIS_2024_21_1_a13,
     author = {Evann Regnault and B\'erenger Bramas},
     title = {SPC5: an efficient {SpMV} framework vectorized using {ARM} {SVE} and x86 {AVX-512}},
     journal = {Computer Science and Information Systems},
     publisher = {mathdoc},
     volume = {21},
     number = {1},
     year = {2024},
     url = {http://geodesic.mathdoc.fr/item/CSIS_2024_21_1_a13/}
}
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Evann Regnault; Bérenger Bramas. SPC5: an efficient SpMV framework vectorized using ARM SVE and x86 AVX-512. Computer Science and Information Systems, Tome 21 (2024) no. 1. http://geodesic.mathdoc.fr/item/CSIS_2024_21_1_a13/