TY  - JOUR
AU  - V. V. Andreeva
AU  - A. Yu. Matrosova
AU  - A. V. Mel'nikov
AU  - A. V. Morozova
TI  - Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
JO  - Prikladnaâ diskretnaâ matematika
PY  - 2009
SP  - 65
EP  - 66
IS  - 10
PB  - mathdoc
UR  - http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/
LA  - ru
ID  - PDM_2009_10_a32
ER  -