%0 Journal Article
%A V. V. Andreeva
%A A. Yu. Matrosova
%A A. V. Mel'nikov
%A A. V. Morozova
%T Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
%J Prikladnaâ diskretnaâ matematika
%D 2009
%P 65-66
%N 10
%I mathdoc
%U http://geodesic.mathdoc.fr/item/PDM_2009_10_a32/
%G ru
%F PDM_2009_10_a32